Current integrated circuit (IC) design is largely dedicated to large systems integrating software and hardware to perform multiple tasks simultaneously, or almost simultaneously. Some of these designs include SoC configurations, typically designed to execute different applications that compete for system resources (e.g., memory, processor time, and bus bandwidth). The large number of operating parameters to consider imposes severe constraints to the software (SW) used for hardware control in the SoC. While the SW may include many parallelized instructions, the more steps included in the SW, the more likely it will be to have redundancies and other undesirable resource sinks embedded in the SW structure. In such circumstances, it is desirable to have a tool that systematically and exhaustively explores the SW structure to provide an optimized source code that improves SoC performance.
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